1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device including a memory cell without a capacitor in which a dynamic memory cell includes a single transistor with a floating body.
2. Description of Related Art
In general, a dynamic random access memory (DRAM) device, which is one type of semiconductor memory device, includes a memory cell that is comprised of a transistor and a capacitor, so that data “0” or “1” is determined depending on whether or not the capacitor is electrically charged. That is, a conventional DRAM device needs a capacitor to store data. However, as the integration density of semiconductor memory devices increases, a memory cell using a capacitor becomes an obstacle in decreasing the layout of the semiconductor memory devices.
Accordingly, a semiconductor memory device in which a memory cell does not require a capacitor, but includes only a transistor, has been recently proposed. This semiconductor memory device includes a memory cell comprising a transistor having a floating body called a “floating body cell (FBC).”
This transistor can store a plurality of carriers in the floating body. The threshold voltage of the transistor varies due to a body effect according to whether or not the carriers are stored, and variations in the threshold voltage of the transistor causes variations in the amount of current through the transistor, thus enabling the determination of data.
Since the carriers stored in the floating body recombine and dissipate after a specific duration of time, the FBC should be periodically refreshed to retain data, so that the FBC can serve as a memory cell of a DRAM.
FIG. 1 is a plan view of a memory cell array block of a conventional semiconductor memory device including an FBC without a capacitor.
In FIG. 1, a memory cell array block 10 includes word lines WL, bit lines BL, memory cells MC, reference word lines RWL0 and RWL1, reference bit lines RBL0 and RBL1, reference memory cells RC0 and RC1, equalizer lines EQL, bit line selectors 12, reference voltage generators 14, and sense amplifiers 16.
The memory cells MC are disposed at intersections of word lines WL arranged in a row direction and bit lines BL arranged in a column direction. Each of the memory cells MC, which includes an NMOS transistor with a floating body, has a gate terminal connected to the word line WL, a drain terminal connected to the bit line, and a source terminal that is grounded.
In order to write data “1” in the memory cell MC, the NMOS transistor is driven in a saturation region. Specifically, when a predetermined voltage (e.g., 1.5 V) is applied to the gate terminal through the word line WL and a voltage higher than the predetermined voltage (e.g., 1.5 V) or the same is applied to the drain terminal through the bit line BL, a large number of electron-hole pairs are created in the floating body near the drain due to impact ionization. In this case, the electrons are absorbed at the drain terminal, but the holes are stored in the floating body.
A hole current generated by the impact ionization is equilibrated with a forward current of a pn-junction between the floating body and the source, so that the floating body reaches an equilibrium state. That is, the state of data “1” is a state where the holes are stored in the floating body.
In order to write data “0” in the memory cell MC, a predetermined voltage (e.g., 1.5 V) is applied to the gate terminal through the word line WL, and a voltage lower than the predetermined voltage (e.g., −1.5 V) is applied to the drain terminal through the bit line BL. Thus, the floating body and the drain, i.e., a p region and an n region are forwardly biased, so that most of the holes stored in the floating body are absorbed at the drain terminal. Accordingly, the state of data “0” is a state where the number of holes stored in the floating body is reduced.
When the data “1” is stored, a lot of holes are stored in the floating body of the NMOS transistor, so that the threshold voltage of the NMOS transistor decreases due to a body effect. When the data “0” is stored, holes stored in the floating body of the NMOS transistor are reduced, so that the threshold voltage of the NMOS transistor increases.
In reading data from the memory cell MC, the NMOS transistor is driven in a linear region. Specifically, when a predetermined voltage (e.g., 1.5 V) is applied to the gate terminal through the word line WL and a voltage (e.g., 0.2 V) required for driving the NMOS transistor in the linear region is applied to the drain terminal through the bit line BL, the NMOS transistor generates a current difference between the bit lines BL due to variation in the threshold voltage caused by a difference in the number of holes stored in the floating body, senses the current difference, and determines data “0” or data “1.” When the data “1” is stored in the memory cell MC, since the threshold voltage of the NMOS transistor is low, a current supplied to the bit line BL during reading of data increases. When the data “0” is stored in the memory cell MC, since the threshold voltage of the NMOS transistor is high, a current supplied to the bit line BL during reading of data decreases.
The reference memory cells RC0 and RC1 are connected between the reference word lines RWL0 and RWL1, which are positioned at both ends of the word lines WL, and the reference bit lines RBL0 and RBL1, which are positioned between the bit lines BL. These reference memory cells RC0 and RC1 store data “0” and data “1,” respectively, in order to generate a reference signal for comparing with data output from the memory cell MC.
The reference bit lines RBL0 and RBL1 are each positioned between a predetermined number of bit lines BL in order to facilitate the precise transmission of the reference signals to the sense amplifiers 16 positioned at both ends of the memory cell array. Thus, each of the reference bit lines RBL0 and RBL1 transmits the reference signals to its near sense amplifier 16.
The reference word lines RWL0 and RWL1 are positioned at both ends of the memory cell array. The reference word line RWL0 serves to select the reference memory cell RC0, and the reference word line RWL1 serves to select the reference memory cell RC1.
The equalizer lines EQL are disposed between the reference word lines RWL0 and RWL1 and the word lines WL, which are positioned at both ends of the memory cell array, and serve to reduce Interaction between the memory cell MC and the reference memory cells RC0 and RC1.
The bit line selectors 12 select one of the bit lines BL in response to a bit line selection signal (not shown) and connect the selected bit line BL to the corresponding sense amplifier 16.
The reference voltage generator 14 generates a voltage in response to a reference signal generated by a combination of currents corresponding to data “0” and data “1” that are applied from the reference memory cells RC0 and RC1, respectively.
The sense amplifier 16 receives a current corresponding to the data of the memory cell MC through the bit lines BL and generates a voltage in response to the received current.
The semiconductor memory devices having the FBC make use of the reference bit lines RBL0 and RBL1 instead of inverted bit lines corresponding to the bit lines BL, unlike conventional semiconductor memory devices. A conventional sense amplifier senses data based on a voltage difference, whereas the sense amplifier 16 of the semiconductor memory device having the FBC senses data based on a current difference. Thus, because the sense amplifier 16 is larger than the memory cell MC, one sense amplifier 16 can service a plurality of bit lines BL. In FIG. 1, one sense amplifier 16 is shared by 8 bit lines BL.
Like the sense amplifier 16, the reference memory cells RC0 and RC1 are also shared. Since the semiconductor memory device having the FBC has no inverted bit line, it needs a reference signal required for determining the data of the memory cell MC. Here, the reference signal is generated by a combination of currents output from the reference memory cells RC0 and RC1 that store data “0” and data “1,” respectively, and output to the reference voltage generator 14 through the reference bit lines RBL0 and RBL1. In FIG. 1, the reference bit lines RBL0 and RBL1, which are connected to the reference memory cells RC0 and RC1, respectively, are vertically interposed between a first set of 8 bit lines BL and another set of 8 bit lines BL and thus shared by 16 bit lines BL.
However, the semiconductor memory device having the FBC without a capacitor as shown in FIG. 1 uses one reference bit line RBL0 or RBL1 shared by a plurality of bit lines BL. Accordingly, there may be a difference in data sensed by the sense amplifier 16 between when data is read from the memory cell MC near the reference bit lines RBL0 and RBL1 and when data is read from the memory cell MC far from the reference bit lines RBL0 and RBL1. In addition, currents corresponding to data of the reference memory cells RC0 and RC1 and the memory cell MC may vary with a change in fabrication process, voltage, or operating temperature, so that an error in data sensed by the sense amplifier 16 may result.